As data rates increase, serial communications links continue to push circuit settings. In receivers with decision feedback equalizer (DFE) settings that have larger values, certain data patterns, such as, for example, alternating 1s and 0s, are susceptible to error propagation on a single bit flip, which is not uncommon. If a single bit flip does occur during transmission of such a sequence, it may then manifest as a contiguous error burst and cause potential data corruption due to cyclic redundancy code (CRC) aliasing.